(kicad_pcb (version 20171130) (host pcbnew "(6.0.0-rc1-dev-1672-g5c3f6f2ab)")

  (general
    (thickness 1.6)
    (drawings 150)
    (tracks 177)
    (zones 0)
    (modules 5)
    (nets 60)
  )

  (page A4)
  (title_block
    (title "8-bit ISA Prototying Board")
    (date 2019-02-07)
    (company "Monotech PCs")
  )

  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (44 Edge.Cuts user)
    (45 Margin user hide)
    (46 B.CrtYd user hide)
    (47 F.CrtYd user hide)
    (48 B.Fab user hide)
    (49 F.Fab user hide)
  )

  (setup
    (last_trace_width 0.254)
    (user_trace_width 1)
    (user_trace_width 1.5)
    (trace_clearance 0.254)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.127)
    (via_size 1)
    (via_drill 0.5)
    (via_min_size 0.6)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.051)
    (solder_mask_min_width 0.25)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010f0_ffffffff)
      (usegerberextensions true)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "gerber"))
  )

  (net 0 "")
  (net 1 A0)
  (net 2 A1)
  (net 3 A2)
  (net 4 A3)
  (net 5 A4)
  (net 6 A5)
  (net 7 A6)
  (net 8 A7)
  (net 9 A8)
  (net 10 A9)
  (net 11 A10)
  (net 12 A11)
  (net 13 A12)
  (net 14 A13)
  (net 15 A14)
  (net 16 A15)
  (net 17 16)
  (net 18 A17)
  (net 19 A18)
  (net 20 A19)
  (net 21 AEN)
  (net 22 IORDY)
  (net 23 D0)
  (net 24 D1)
  (net 25 D2)
  (net 26 D3)
  (net 27 D4)
  (net 28 D5)
  (net 29 D6)
  (net 30 D7)
  (net 31 IOCHK)
  (net 32 GND)
  (net 33 OSC)
  (net 34 +5V)
  (net 35 ALE)
  (net 36 TC)
  (net 37 ~DACK2)
  (net 38 IRQ3)
  (net 39 IRQ4)
  (net 40 IRQ5)
  (net 41 IRQ6)
  (net 42 IRQ7)
  (net 43 CLK)
  (net 44 ~DACK0)
  (net 45 DRQ1)
  (net 46 ~DACK1)
  (net 47 DRQ3)
  (net 48 ~DACK3)
  (net 49 ~IOR)
  (net 50 ~IOW)
  (net 51 ~MEMR)
  (net 52 ~MEMW)
  (net 53 +12V)
  (net 54 CARDSEL)
  (net 55 -12V)
  (net 56 DRQ2)
  (net 57 -5V)
  (net 58 IRQ2)
  (net 59 RESET)

  (net_class Default "This is the default net class."
    (clearance 0.254)
    (trace_width 0.254)
    (via_dia 1)
    (via_drill 0.5)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net +12V)
    (add_net +5V)
    (add_net -12V)
    (add_net -5V)
    (add_net 16)
    (add_net A0)
    (add_net A1)
    (add_net A10)
    (add_net A11)
    (add_net A12)
    (add_net A13)
    (add_net A14)
    (add_net A15)
    (add_net A17)
    (add_net A18)
    (add_net A19)
    (add_net A2)
    (add_net A3)
    (add_net A4)
    (add_net A5)
    (add_net A6)
    (add_net A7)
    (add_net A8)
    (add_net A9)
    (add_net AEN)
    (add_net ALE)
    (add_net CARDSEL)
    (add_net CLK)
    (add_net D0)
    (add_net D1)
    (add_net D2)
    (add_net D3)
    (add_net D4)
    (add_net D5)
    (add_net D6)
    (add_net D7)
    (add_net DRQ1)
    (add_net DRQ2)
    (add_net DRQ3)
    (add_net GND)
    (add_net IOCHK)
    (add_net IORDY)
    (add_net IRQ2)
    (add_net IRQ3)
    (add_net IRQ4)
    (add_net IRQ5)
    (add_net IRQ6)
    (add_net IRQ7)
    (add_net OSC)
    (add_net RESET)
    (add_net TC)
    (add_net ~DACK0)
    (add_net ~DACK1)
    (add_net ~DACK2)
    (add_net ~DACK3)
    (add_net ~IOR)
    (add_net ~IOW)
    (add_net ~MEMR)
    (add_net ~MEMW)
  )

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    (pad 62 thru_hole oval (at 2.54 76.2 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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      (net 30 D7))
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      (net 32 GND))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 31 IOCHK))
  )

  (module Custom:Conn_Edge_PCB_ISA8 (layer F.Cu) (tedit 5A57C7D9) (tstamp 5C5BFCC4)
    (at 114.935 135.255)
    (descr "Connector, PCB Edge, ISA8")
    (tags "CONN BUS ISA")
    (path /5C5BFBAF)
    (fp_text reference J1 (at -36.83 -6.35) (layer F.Fab) hide
      (effects (font (size 1.016 1.016) (thickness 0.2032)))
    )
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      (effects (font (size 1.016 0.9144) (thickness 0.2032) italic))
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    (fp_line (start 40.64 -4.7625) (end -40.64 -4.7625) (layer Dwgs.User) (width 0.254))
    (pad 1 connect rect (at 38.1 0) (size 1.778 7.62) (layers B.Cu B.Mask)
      (net 32 GND))
    (pad 2 connect rect (at 35.56 0) (size 1.778 7.62) (layers B.Cu B.Mask)
      (net 59 RESET))
    (pad 3 connect rect (at 33.02 0) (size 1.778 7.62) (layers B.Cu B.Mask)
      (net 34 +5V))
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      (net 58 IRQ2))
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      (net 57 -5V))
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      (net 56 DRQ2))
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      (net 55 -12V))
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      (net 54 CARDSEL))
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      (net 53 +12V))
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      (net 52 ~MEMW))
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      (net 43 CLK))
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      (net 38 IRQ3))
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      (net 34 +5V))
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      (net 33 OSC))
    (pad 31 connect rect (at -38.1 0) (size 1.778 7.62) (layers B.Cu B.Mask)
      (net 32 GND))
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      (net 31 IOCHK))
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      (net 30 D7))
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      (net 29 D6))
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      (net 23 D0))
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      (net 21 AEN))
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      (net 20 A19))
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      (net 17 16))
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      (net 14 A13))
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      (net 13 A12))
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      (net 12 A11))
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      (net 11 A10))
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      (net 8 A7))
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      (net 5 A4))
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      (net 4 A3))
    (pad 60 connect rect (at -33.02 0) (size 1.778 7.62) (layers F.Cu F.Mask)
      (net 3 A2))
    (pad 61 connect rect (at -35.56 0) (size 1.778 7.62) (layers F.Cu F.Mask)
      (net 2 A1))
    (pad 62 connect rect (at -38.1 0) (size 1.778 7.62) (layers F.Cu F.Mask)
      (net 1 A0))
  )

  (gr_text "8-bit ISA\nPrototype\nBoard" (at 71.12 128.016) (layer B.SilkS) (tstamp 5C5DDB5C)
    (effects (font (size 1 0.8) (thickness 0.15)) (justify mirror))
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